Architect Labs Builds Redwood AI Accelerator in Two Weeks

Architect Labs has demonstrated an AI-driven design system that generated Redwood, a functional inference accelerator running on Field Programmable Gate Array (FPGA) hardware, in less than 14 days. Two human architects initiated the process by providing high-level specifications. The startup's AI system then automatically generated the performance model, register-transfer level (RTL) code, firmware, drivers, compute kernels, and verification environments. The resulting design achieved over 95 percent code and functional coverage across hardware testing and commercial design software.

The prototype, dubbed Redwood Nano, currently runs models such as Llama and Qwen on FPGA hardware. During testing with the Qwen3 0.6B model, the FPGA-based Redwood Nano achieved a processing speed of 12.1 tokens per second. While this trails the Nvidia Jetson Orin Nano's speed of 28 tokens per second, Architect Labs projects significant gains if the design is manufactured as physical silicon. Using simulations for Samsung's 8nm manufacturing process, the company estimates Redwood would reach 49 tokens per second while consuming roughly half the power of the Nvidia baseline, yielding a 3.4-times improvement in performance per watt.

In a novel test of recursive self-improvement, the researchers ran Qwen3 on the Redwood hardware and connected it back to their design platform. The model successfully identified software kernel optimizations and timing improvements for future hardware iterations. For chip designers and AI practitioners, this automated workflow could solve a major industry bottleneck. Instead of spending years developing custom silicon for AI models that become obsolete before production, engineering teams could modify specifications, redesign components, and verify updates on FPGA hardware in under 48 hours.