OpenAI Uses Its Own LLMs to Design Jalapeño Chip

OpenAI has fully unveiled its debut AI accelerator chip, Jalapeño, which was developed from initial concept to physical silicon in less than 20 months. The chip delivers up to 13.4 petaflops of 4-bit compute and features 232 gigabytes of advanced memory with a bandwidth of 15.4 terabytes per second. In benchmarks, Jalapeño reduced end-to-end latency by up to 3.6x compared to Nvidia's GB300 processor while consuming less power. OpenAI plans to deploy the hardware in pods containing 2,048 chips.

A small team of fewer than 100 people designed the chip by leveraging OpenAI's own large language models alongside partner Broadcom, which handled the physical backend implementation. The team used Accelerated Hardware Synthesis (XLS), an open-source toolchain, to write code in C++ and DSLX before converting it to Verilog. Early in the project, the team used OpenAI's o3 model, but later transitioned to precursors of GPT-6 Astra. According to OpenAI staff, these advanced models can write Verilog directly without translation.

The integration of LLMs yielded massive efficiency gains in both hardware and software optimization. Using AI-guided physical design, OpenAI achieved a 10 percent area reduction for its matrix multiplication units. On the software side, the team used internal AI models to optimize code for DeepSeek's multi-head latent attention kernel benchmark, boosting performance from 0.31 percent of the chip's theoretical ceiling to 88.94 percent in just 40 hours.

For hardware engineers and chip designers, this development signals a paradigm shift where LLMs act as force multipliers. While human engineers remain the final arbiters, AI-driven automation compresses the time between first register-transfer level code and tapeout to just nine months. As future models like Astra gain the ability to operate proprietary design tools directly, small engineering teams will be able to iterate on complex custom silicon at speeds previously reserved for industry giants.